1. Field of the Invention
The present invention relates to a semiconductor memory circuit and, more particularly to a dynamic type random access memory (DRAM) fabricated on a semiconductor substrate.
2. Description of the Related Art
Dynamic memory circuits have been widely utilized as large capacity semiconductor memories in various fields. The dynamic memory circuit is generally constructed in such a manner that one-transistor type memory cells are arranged in a matrix form of rows and columns together with word lines and bit lines arranged in rows and columns, respectively.
According to the conventional technique, the number of memory cells connected to one bit line increases as the memory capacity increases. Consequently, a stray capacitance of each bit line increases to cause various problems. First, when the sense amplifiers are activated, the bit lines need to be charged or discharged to a power supply potential Vcc or a ground potential Vss. In this regard, the increase in the stray capacitances of the bit lines cause an increase in the time required for charging and discharging. If the respective pairs of bit lines are not sufficiently amplified, that is, if charging or discharging is not sufficiently effected, it is impossible to enable a column selection circuit so as to connect the selected pair of bit lines to a pair of common data lines. This is because, when the common data lines are connected to bit lines, the charges on the common data lines may flow into the bit lines to destroy the stored information. As a consequence, the time at which the data is output from an output terminal is delayed, which results in a lower operation speed. Secondly, the increase in the bit line stray capacitances causes an increase in the charging and discharging current during an active period, thus causing problems, for example, floating of the ground potential at an internal ground wiring, a lowering in the power supply potential, and generation of noise between the bit lines. Particularly, the floating of the ground potential during the active period causes noise due to operations of peripheral circuits such as an output circuit, the column selection circuit, and a potential of the non-selected word lines undesirably exceeds a threshold voltage of memory cell transistors or more, storage capacitors of the non-selected memory cells are erroneously connected to the bit lines, resulting in destruction of the stored data.